`timescale 1ns / 1ps
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// Company: 
// Engineer: 
// 
// Create Date: 2020/11/09 15:47:19
// Design Name: 
// Module Name: MUX4T1_32
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
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module MUX4T1_32 (
    input  wire [ 1:0] s,
    input  wire [31:0] I0,
    input  wire [31:0] I1,
    input  wire [31:0] I2,
    input  wire [31:0] I3,
    output wire [31:0] o
);

  wire s0 = s == 2'b00;
  wire s1 = s == 2'b01;
  wire s2 = s == 2'b10;
  wire s3 = s == 2'b11;

  assign o = {32{s0}} & I0 | {32{s1}} & I1 | {32{s2}} & I2 | {32{s3}} & I3;
endmodule
